2.2.2.1 EEPROM Boot Process
If the target device has an application EEPROM (an EEPROM that contains both header and application data), and
if the header portion of the EEPROM content is valid, the EEPROM application code is downloaded to on-chip RAM.
During the download process, the RAM is mapped to data space, and the boot code that orchestrates the download
is part of the on-chip firmware housed in on-chip ROM. Also, while the application code is being downloaded, the
TAS1020A remains disconnected from the USB bus.
When the download is complete, the firmware sets the ROM disable bit SDW. The setting of this bit maps the RAM
from data space to program space, starting address 0x0000. Having set bit SDW, the firmware then branches to
address 0x0000, which is the reset entry point for the application code. The application code is now running.
The application code then switches on the PUR output. The PUR output pin is connected, through a resistor, to the
positive (DP) line of the differential USB bus. Switching PUR on informs the host that a full speed (12 Mb/s) device
is present on the bus. In the enumeration procedure that follows, the application code reports its run-time device
descriptor set. Following enumeration, the device is actively running its application.