U-Boot SPL 2019.07 (Dec 15 2022 - 10:28:31 +0800) Strap register: 0x7fffdf43 Board is non secure $SPL: 5.04L.02@422426 $ Apply trim code 0x8 reg 0x20 from otp to LDO controller... nand flash device id 0xc2da9091, total size 256MB block size 128KB, page size 2048 bytes, spare area 108 bytes ECC BCH-8 FFinit done find magic number 0x75456e76 at address 0x40000 CRC mismatch len = 16384 computed fec7aa93 expected 48e274bf find magic number 0x75456e76 at address 0xae000 CRC mismatch len = 16384 computed fec7aa93 expected 48e274bf no mcb specified explicitly, use safe mode blob not found for magic 0xcb00cb sel 0x1607! FFinit find magic number 0xcb00cb at address 0x45000 reading blob from 0x45000 offset 0x286c len 608 digest sha256 OK FFinit find magic number 0x64447233 at address 0x20000 reading blob from 0x20000 offset 0xc len 34756 digest sha256 OK mcb selector 0x1607 checksum 0xf70ef8ae safe_mode 1
MemsysInit hpg0_generic 3.13.0.0 20191119 DDR3 8529DB50 80180000 801A0000 00000000 00000000 00706E10 MCB rev=0x00020501 Ref ID=0x06E10 Sub Bld=0x007 Dram Timing 11-11-11
start of memsys_begin mc_cfg_init(): Initialize the default values on mc_cfg init_memc_dram_profile(): Initializing MEMC DRAM profile --------------------------------------------------------------- MEMC DRAM profile (memc_dram_profile_struct) values: dram_type = DDR3 ==================================================== PART values: part_speed_grade = 1600 CL11 part_size_Mbits = 8192 (DRAM size in MegaBits) part_row_bits = 16 (number of row bits) part_col_bits = 11 (number of column bits) part_ba_bits = 3 (number of bank bits) part_width_bits = 8 (DRAM width in bits) NUMER OF PARTS: part_num = 2 (Number of parts) TOTAL values: total_size_Mbits = 16384 (DRAM size in MegaBits) total_cs_bits = 0 (number of cs bits, for dual_rank mode) total_width_bits = 16 (DRAM width in bits) total_burst_bytes = 16 (Number of bytes per DRAM access) total_max_byte_addr = 0x7fffffff (Maximum/last DRAM byte address) (Number of bits in total_max_byte_addr is 31) (i.e. total_max_byte_addr goes from bit 0 to bit 30) ddr_2T_mode = 0 ddr_hdp_mode = 0 large_page = 1 ddr_dual_rank = 0 cs_mode = 0 MEMC timing (memc_dram_timing_cfg_struct) values: ==================================================== MC_CHN_TIM_TIM1_0 register fields: tCwl = 8 tRP = 11 tCL = 11 tRCD = 11 MC_CHN_TIM_TIM1_1 register fields: tCCD_L = 4 tCCD = 4 tRRD_L = 5 tRRD = 5 MC_CHN_TIM_TIM1_2 register fields: tFAW = 24 tRTP = 6 tRCr = 39 MC_CHN_TIM_TIM1_3 register fields: tWTR_L = 6 tWTR = 6 tWR_L = 12 tWR = 12 MC_CHN_TIM_TIM2 register fields: tR2R = 0 tR2W = 2 tW2R = 2 tW2W = 0 tAL = 0 tRFC = 280 ==================================================== %1 SSC enabled
Poll PHY Status register PHY Status= 1 Disable Auto-Refresh [80180200] = 0x00000305 End of memsys_begin Add/Ctl Alignment Coarse Adj=0x087 deg, cmd steps=0x0E0 reg 0x801A0090 set to VDL 0x055 with Fine Adj=0x01 deg reg 0x801A0094 set to VDL 0x055 with Fine Adj=0x01 deg reg 0x801A0098 set to VDL 0x055 with Fine Adj=0x01 deg reg 0x801A009C set to VDL 0x055 with Fine Adj=0x01 deg reg 0x801A00A0 set to VDL 0x055 with Fine Adj=0x01 deg reg 0x801A00A4 set to VDL 0x055 with Fine Adj=0x01 deg reg 0x801A00A8 set to VDL 0x055 with Fine Adj=0x01 deg reg 0x801A00AC set to VDL 0x055 with Fine Adj=0x01 deg reg 0x801A00B0 set to VDL 0x055 with Fine Adj=0x01 deg reg 0x801A00B4 set to VDL 0x055 with Fine Adj=0x01 deg reg 0x801A00B8 set to VDL 0x055 with Fine Adj=0x01 deg reg 0x801A00BC set to VDL 0x055 with Fine Adj=0x01 deg reg 0x801A00C0 set to VDL 0x055 with Fine Adj=0x01 deg reg 0x801A00C4 set to VDL 0x055 with Fine Adj=0x01 deg reg 0x801A00C8 set to VDL 0x055 with Fine Adj=0x01 deg reg 0x801A00CC set to VDL 0x055 with Fine Adj=0x01 deg reg 0x801A00D0 set to VDL 0x055 with Fine Adj=0x01 deg reg 0x801A00D4 set to VDL 0x055 with Fine Adj=0x01 deg reg 0x801A00D8 set to VDL 0x055 with Fine Adj=0x01 deg reg 0x801A00DC set to VDL 0x055 with Fine Adj=0x01 deg reg 0x801A00E0 set to VDL 0x055 with Fine Adj=0x01 deg reg 0x801A00E4 set to VDL 0x055 with Fine Adj=0x01 deg reg 0x801A00E8 set to VDL 0x055 with Fine Adj=0x01 deg reg 0x801A00EC set to VDL 0x055 with Fine Adj=0x01 deg reg 0x801A00F0 set to VDL 0x055 with Fine Adj=0x01 deg reg 0x801A00F4 set to VDL 0x055 with Fine Adj=0x01 deg reg 0x801A00F8 set to VDL 0x055 with Fine Adj=0x01 deg reg 0x801A00FC set to VDL 0x055 with Fine Adj=0x01 deg reg 0x801A0100 set to VDL 0x055 with Fine Adj=0x01 deg reg 0x801A0108 set to VDL 0x055 with Fine Adj=0x01 deg reg 0x801A010C set to VDL 0x055 with Fine Adj=0x01 deg HP RX TRIM itrim = 0x0 lstrim = 0xB
ZQ Cal HP PHY R in Ohm P: Finger=0x364 Term=0x7C Drv=0x27 N: Finger=0x336 Term=0x75 Drv=0x27
start of memsys_end [80180004] = 0x8130071f [80180010] = 0x00000007 end of memsys_end ### ERROR ### Please RESET the board ###
судя по логу процессор не видит озу. напряжения на озу 1.2в 2.4в 0.6в есть. прогрев озу результата не дал. собственно вопрос возможно что озу умерла или частичный отвал процессора.
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