entity serializer is
port
(
-- fx2lp connection
fx2_data : inout std_logic_vector(7 downto 0);
fx2_clk : in std_logic; -- clock for data exchange from GPIF

fx2_read_write_switch : in std_logic; -- write from fx2lp when low
fx2_cmd_dat_switch : in std_logic; -- use dat-line when low
fx2_ready_from_epm : out std_logic; -- ready to next from epm when low
fx2_low_speed_switch : in std_logic; -- low initial speed when low

-- emmc connection for 3.3 and 1.8
emmc_clk33 : out std_logic;
emmc_cmd33 : inout std_logic;
emmc_dat33 : inout std_logic;
emmc_clk18 : out std_logic;
emmc_cmd18 : inout std_logic;
emmc_dat18 : inout std_logic;

-- epm system connection
epm_master_clk : in std_logic; -- input from fx2lp 48MHz
epm_master_clk_ext : in std_logic; -- input from quartz-gen 50MHz
epm_clk_select_jumper : in std_logic; -- input from quartz when low
epm_clk_divby2_jumper : in std_logic; -- 48MHz -> 24MHz when low
slow_clk_divby2_jumper : in std_logic -- 400kHz -> 200kHz when low
-- maybe reset?
);
end serializer;

architecture serial_convert of serializer is

signal master_clock : std_logic := '0'; -- isp clock from domains
signal clk_counter : unsigned(7 downto 0):=(others=>'0');
signal isp_clock : std_logic := '0'; -- isp clock slow for init


signal reg_tx_data1 : std_logic_vector( 7 downto 0 );
signal reg_tx_data2 : std_logic_vector( 7 downto 0 );
signal reg_rcv_dat0_1 : std_logic_vector( 7 downto 0 );
signal reg_rcv_dat0_2 : std_logic_vector( 7 downto 0 );
signal reg_rcv_cmd1 : std_logic_vector( 7 downto 0 );
signal reg_rcv_cmd2 : std_logic_vector( 7 downto 0 );


begin

clock_switch_fx2: process(epm_master_clk)
begin
if epm_clk_select_jumper /= '0' then
if epm_clk_divby2_jumper = '0' then
if (rising_edge(epm_master_clk)) then
master_clock <= NOT master_clock;
end if;
else
master_clock <= epm_master_clk;
end if;
end if;
end process clock_switch_fx2;
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clock_switch_quartz: process(epm_master_clk_ext)
begin
if epm_clk_select_jumper = '0' then
if epm_clk_divby2_jumper = '0' then
if (rising_edge(epm_master_clk_ext)) then
master_clock <= NOT master_clock;
end if;
else
master_clock <= epm_master_clk_ext;
end if;
end if;
end process clock_switch_quartz;
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clock_divider: process(master_clock)
begin
if(rising_edge(master_clock)) then
clk_counter <= clk_counter + 1;
end if;
end process clock_divider;
------------------------------------------------------
isp_clock_switch: process(master_clock)
begin
if fx2_low_speed_switch = '0' then
if slow_clk_divby2_jumper = '0' then
isp_clock <= clk_counter(7);
else
isp_clock <= clk_counter(6);
end if;
else
isp_clock <= master_clock;
end if;
end process isp_clock_switch;
------------------------------------------------------
fx2_parallel_rw: process(fx2_clk)
begin
.......................................