Добавлено (05.06.2026, 16:22:49) --------------------------------------------- После подмены разделов в прошивку которую мне любезно предоставили , получаю лог похожий на тот что был но с перезагрузкой.
Board ID = 3 Set cpu clk to 24M Set clk81 to 24M CPU clk: 1200 MHz Set clk81 to 166.6M eMMC boot @ 0 sw8 s OTP_ARB=00000001 DDR driver_vesion: LPDDR4_PHY_V_0_1_11 build time: Apr 14 2019 10:28:31 board id: 3 Load FIP HDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part : 0 fw parse done Load ddrfw from eMMC, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0 Load ddrfw from eMMC, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0 PIEI prepare done Cfg max: 5, cur: 1. Board id: 255. Force loop cfg DDR4 probe ddr clk to 1200MHz Load ddrfw from eMMC, src: 0x00014200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of read enable training INFO : End of fine write leveling INFO : STREAM 0x0049000 - 0x0000000 0x0000000 INFO : STREAM 0x0402000 - INFO : ERROR : Training has failed! 1D training failed Cfg max: 5, cur: 2. Board id: 255. Force loop cfg DDR3 probe ddr clk to 912MHz Load ddrfw from eMMC, src: 0x0002c200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of read enable training INFO : End of fine write leveling INFO : End of read dq deskew training INFO : End of MPR read delay center optimization INFO : End of Write leveling coarse delay INFO : End of write delay center optimization INFO : End of read delay center optimization INFO : End of max read latency training INFO : Training has run successfully! 1D training succeed auto size-- 65535DDR cs0 size: 1024MB DDR cs1 size: 1024MB DMC_DDR_CTRL: 0020001bDDR size: 2048MB cs0 DataBus test pass cs1 DataBus test pass cs0 AddrBus test pass cs1 AddrBus test pass pre test bdlr_100_average==502 bdlr_100_min==502 bdlr_100_max==502 bdlr_100_cu r==502 aft test bdlr_100_average==502 bdlr_100_min==502 bdlr_100_max==502 bdlr_100_cu r==502 100bdlr_step_size ps== 507 result report boot times 0ddr scramble enabled Enable ddr reg access 00000000 emmc switch 3 ok BL2: rpmb counter: 0x0000001c 00000000 emmc switch 0 ok Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part : 0 Load BL3X from eMMC, src: 0x0006c200, des: 0x0175c000, size: 0x00110000, part: 0 bl2z: ptr: 05129328, size: 00001e48 0.0;0.0;M3 CHK:0;cm4_sp_mode 0 MVN_1=0x12000000 MVN_2=0x00000000 [Image: g12a_v1.1.3383-4a790d5 2019-04-16 15:22:56 luan.yuan@droid15-sz] OPS=0x40 ring efuse init 28 0c 40 00 01 23 17 00 00 03 38 37 30 4b 52 50 [0.017123 Inits done] secure task start! high task start! low task start! run into bl31 NOTICE: BL31: v1.3(release):740cfac NOTICE: BL31: Built : 16:37:27, Apr 3 2019 NOTICE: BL31: G12A secure boot! NOTICE: BL31: BL33 decompress pass INFO: BL3-2: ATOS-V2.4-214-g878b640 #1 Mon Feb 25 11:00:18 UTC 2019 arm INFO: BL3-2: Chip: G12A Rev: C (28:C - 40:2) INFO: BL3-2: crypto engine DMA INFO: BL3-2: secure time TEE INFO: BL3-2: CONFIG_DEVICE_SECURE 0xb200000e
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, получаю лог похожий на тот что был но с перезагрузкой.
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